1. Field of The Invention
This invention relates to an oscillator circuit and more particularly, to an oscillator circuit which uses a D type flip-flop.
2. Description of the Prior Art
In telecommunications circuits involving the transmission of signals using digital techniques, it is often necessary to provide a master clock frequency of 1.536 MHz. It is often also necessary in such circuits to provide the frequency of 768 KHz as well as the complement of that frequency as clocking inputs to various counters.
The D type flip-flop is a common choice for dividing the master clock frequency by two to provide the 768 KHz frequency and its complement. D type flip-flops are typically available in an integrated circuit package known as a dual D which includes two such flip-flops. As only one of the flip flops is needed to divide the master clock frequency by two, the other half of the integrated circuit package is not used.
In addition, this usage of the dual D package requires another active device to generate the master clock frequency. It is, however, desirable to fully utilize the dual D package to not only divide the master clock frequency by two and provide the desired complementary outputs, but also to generate that clock frequency. The circuit of the present invention provides that function.